1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, the present invention relates to the core structure layout of phase-change semiconductor memory devices.
A claim of priority is made to Korean Patent Application No. 10-2005-0053550, filed on Jun. 21, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
A phase-change random access memory (PRAM), also known as an Ovonic Unified Memory (OUM), includes a phase-change material such as a chalcogenide alloy which is responsive to heat so as to be stably transformed between crystalline and amorphous states. Such a PRAM is disclosed, for example, in U.S. Pat. Nos. 6,487,113 and 6,480,438.
The phase-change material of the PRAM exhibits a relatively low resistance in its crystalline state, and a relatively high resistance in its amorphous state. In conventional nomenclature, the low-resistance crystalline state is referred to a ‘set’ state and is designated logic “0”, while the high-resistance amorphous state is referred to as a ‘reset’ state and is designated logic “1”.
The terms “crystalline” and “amorphous” are relative terms in the context of phase-change materials. That is, when a phase-change memory cell is said to be in its crystalline state, one skilled in the art will understand that the phase-change material of the cell has a more well-ordered crystalline structure when compared to its amorphous state. A phase-change memory cell in its crystalline state need not be fully crystalline, and a phase-change memory cell in its amorphous state need not be fully amorphous.
Generally, the phase-change material of a PRAM is reset to an amorphous state by heating the material in excess of its melting point temperature for a relatively short period of time. On the other hand, the phase-change material is set to a crystalline state by heating the material below its melting point temperature for a longer period of time.
The speed and stability of the phase-change characteristics of the phase-change material are critical to the performance characteristics of the PRAM. As suggested above, chalcogenide alloys have been found to have suitable phase-change characteristics, and in particular, a compound including germanium (Ge), antimony (Sb) and tellurium (Te) (e.g., Ge2Sb2Te5 or GST) exhibits a stable and high speed transformation between amorphous and crystalline states.
FIGS. 1A and 1B illustrate a memory cell 10 in a ‘set’ state and in a ‘reset’ state, respectively, and FIG. 2 is an equivalent circuit diagram of the memory cell 10 of FIGS. 1A and 1B. As shown, the memory cell 10 includes a phase-change element 11 and an access transistor 20 connected in series between a bit line BL and a reference potential (e.g., ground). Also, as shown, a gate of the access transistor 20 is connected to a word line.
It should be noted that the structure of the phase-change element 11 is presented as an example only, and that other structures may be possible. Similarly, the connections illustrated in FIGS. 1A, 1B and 2 are presented as examples only, and other configurations are possible. For example, the memory cell 10 may include the phase-change element 11 and a diode (not shown) connected in series between the bit line BL and the word line WL.
In each of FIGS. 1A and 1B, the phase-change element 11 includes a top electrode 12 formed on a phase-change material 14. In this example, the top electrode 12 is electrically connected to a bit line BL of a PRAM memory array (not shown). A conductive bottom electrode contact (BEC) 16 is formed between the phase-change material 14 and a conductive bottom electrode 18. The access transistor 20 is electrically connected between the bottom electrode 18 and the reference potential, and the gate of the access transistor 20 is electrically connected to a word line WL of the PRAM cell array (not shown).
In FIG. 1A, the phase-change material 14 is illustrated as being in its crystalline state. As mentioned previously, this means that the memory cell 10 is in a low-resistance ‘set’ state or logic 0 state. In FIG. 1B, a portion of the phase-change material 14 is illustrated as being amorphous. Again, this means that the memory cell 10 is in a high-resistance ‘reset’ state or logic 1 state.
The set and reset states of the memory cell 10 of FIGS. 1A and 1B are establish by controlling the magnitude and duration of current flow through the BEC 16. That is, as shown in FIG. 2, the memory cell 10 is activated (or accessed) by applying a LOW level voltage to the word line WL. When activated, the phase-change element 11 is programmed according to the voltage of the bit line BL. More specifically, the bit line BL voltage is controlled to establish a programming current which causes the BEC 16 to act as a resistive heater which selectively programs the phase-change material 14 in its ‘set’ and ‘reset’ states.
FIG. 3 is a view showing the core structure layout of a conventional phase change memory device 300.
Referring to FIG. 3, the phase change memory 300 includes a plurality of memory cell blocks CBLK, a plurality of word line driving blocks WDU, a plurality of bit line selection blocks YPASS, and a plurality of discharge blocks YDCU. Each of the word line driving blocks WDU includes word line driving circuits (not shown) for driving word lines (not shown) of the memory cell blocks CBLK. Each of the bit line selection blocks YPASS includes bit line selection circuits YSEL<1–n> which are responsive to selection signals Y<1–n> to select respective bit lines BL<1–n> of the memory cell blocks CBLK. Likewise, each of the discharge blocks YDCU includes discharge circuits BLD<1–n> which are responsive to inverted selection signals Y<1–n>b to discharge the respective bit lines BL<1–n>.
FIG. 3 also illustrates block areas which may contain, for example, a column decoder YDEC, a sense amplification circuit SA, and a write driver WD.
As shown in FIG. 3, the bit line selection circuits YSEL<1–n> and the discharge circuits BLD<1–n> are implemented by MOS transistors. The MOS transistors of the bit line selection circuits YSEL<1–n> are inserted in the respective bit lines BL<1–n>, while the MOS transistors of the discharge circuits BLD<1–n> are connected between the respective bit lines BL<1–n> and a reference potential VSS e.g., ground. As such, a pair of MOS transistors (a bit line selection transistor and a discharge transistor) is connected to each of the bit line BL<1–n> adjacent the memory block CBLK containing the bit lines BL<1–n>. It is difficult (and sometimes impossible) from a layout perspective to place these pair of MOS transistors at the end of each bit line BL, particularly as the bit lines BL<1–n> are brought closer together to increase memory density.